2026年秋季实习生
实习时间：2026年7月-12月（共6个月，每周3-5天）
实习对象：2027届毕业生

要求：
1. Can work at least 4 days a week and last for at least 6 months.
2. Self-Motivated with strong passion for programming and learning.
3. Postgraduate student majored in Computer Science, Computer Software Engineering or Electrical Engineering, etc.
4. You should have knowledge and proficiency in at least one of the following areas:
- Good at C/C++ programming and debugging
- Experience in development with Python, Groovy, Java, Perl or other languages
- Experience with basic Linux commands
- C# programming and asp.net website development
- Familiar with Git/GitHub workflows and AI programming tools (e.g. GitHub Copilot, etc.)
5. Obtaining of any following skills or experiences is a plus:
- Experience in Machine Learning/AI modeling application
- Understanding of Continuous Integration System Implementation (e.g. Jenkins, GitHub Action, etc.)
- Experience in x86 assembly, UEFI, BIOS, firmware development
- Comfortable with working with PC platforms and devices
6. Fluent in both written and verbal English"

工作内容：
"We are seeking highly motivated BIOS Tool and BV Engineering intern to join our team. In this role, will assist the Firmware/Software Engineers in the following areas –

1. Develop and maintain BIOS related tools/utilities/websites and design documents. Deploy AI modeling application in BIOS tools.
2. Develop and maintain BIOS/Firmware CI automation test and BIOS Verification test scripts/database.
3. Set up CI automation test environment and systems. Report and trouble shoot issues.
4. Support BIOS/Firmware issue regression, unite test, issue triage and debug."

WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_


Front-End Silicon Design & Integration (FEINT) Engineer
Location: Shanghai


The role:
A Front-End Silicon Design and Integration (FEINT) Engineering role in our GFX Memory Controller IP (GMCIP) team. GFX Memory controller provides high performance functions to System on Chip (SoC) products across all AMD business units such as GPU AI accelerators, graphics and gaming. Our FEINT engineers will perform RTL synthesis and PPA analysis in order to improve the QoR of RTL designs. They will also create, adopt and automate RTL static design rule checks, perform ECO and LEC checks.

The person:
A talented FEINT engineer with strong records of technical ownership and execution to drive synthesis, PPA analysis, Power redux, ECO, and static verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability.
Key responsibilities:
• Develop RTL synthesis strategy and scripts to perform synthesis, timing path analysis and PPA analysis (performance, power, area) at subsystem level as well as at block level RTL designs to drive for continued improvement of QoR (quality of result)
• Develop power redux strategy such as hierarchical CG (clock gating) at multiple levels including RTL and gate level, to ensure power target attainment
• Develop ECO strategy, perform netlist and/or conformal assisted RTL ECOs, perform LEC on resulting netlists and resolve discrepancies
• Develop, adopt and automate RTL static design rule checks in collaboration with Integration and Physical design teams, triage and debug design rule violations with RTL design team, support IP integration with SoC team
• Develop and adopt FEINT design and verification infrastructure, methodology and tools
Preferred experience:
• Proven understanding of RTL design, synthesis, and ECO principles
• Excellent knowledge with FE design tools such as Design/Fusion Compiler, Prime Time, Power Artist, PtPx, etc.
• Proficient with Verilog, C/C++ and other scripting languages (e.g. Tcl, Ruby, Perl, Python and Makefile)
• Excellent skills with Unix/Linux environment
• Familiar with RTL coding techniques for competitive PPA-measured QoR
• Familiar with RTL coding style for clean check on design rules (LINT, CDC, etc.)
• Good understanding of gate level circuit design and physical level design concept and methodology
• Familiar with VCS/Verdi
• Excellent communication skills in English (both written and oral)
• Self motivated, and committed to achievement
Academic credentials:
• Bachelor's Degree or Master's Degree in Electrical Engineering, Computer Engineering, or possibly a related field
• Master's Degree preferred
• BSc with a minimum of 5 years relevant experience, or MSc with a minimum of 3 years
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DV

MTS SILICON DESIGN ENGINEER 
 
THE ROLE:
The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.  
 
THE PERSON: 
You have a passion for modern, complex processor architecture, digital design, and verification in