Process Integration Intern

About the Role We are seeking a Process Integration Intern to support advancedsemiconductor device and materials research, with a focus on gate stack (HKMG)and work function tuning technologies used in FinFET, GAA, and DRAM devices.This role offers hands-on exposure to technology trend analysis, materialevaluation, and device-level data interpretation in a fast-paced R&Denvironment. ________________________________________ Key Responsibilities ?Conduct technology landscape studies on gate stack and work function tuningmaterials using publicly available literature and patents ? Analyze developmenttrends, material properties, advantages, and limitations across differentintegration approaches ? Support PIE engineers and cross-functional teams byreviewing device-level characterization data (e.g., MOSCAP) ? Identifypotential material-related risks and failure mechanisms, and propose mitigationstrategies ? Summarize HKMG technology developments, including metal stacks(e.g., TiN, Mo, W, Ru) and dipole tuning approaches ? Build a short-loop HKMGprocess flow, identifying key steps, integration challenges, and potentialsolutions ? Develop a MOSCAP-based DFMEA, linking test items (e.g., CV,leakage, breakdown) with material-driven failure mechanisms ? Providerecommendations for test planning and process optimization for high-k materials(e.g., HfO-based stacks) ________________________________________ ExpectedDeliverables ? A structured technology and material roadmap for HKMG and workfunction tuning ? Identification of key technical risks and bottlenecks acrossdifferent integration paths ? A complete MOSCAP DFMEA framework ?Recommendations on test strategies and material optimization________________________________________ Impact of the Role ? Support futuretechnology selection and accelerate decision-making on gate stack materials ?Enhance understanding of device-level failure mechanisms related to HKMG andMOSCAP behavior ? Build a structured knowledge base to improve evaluationefficiency and material risk assessment________________________________________ Qualifications ? Master’s degree (orabove) in Electrical Engineering, Materials Science, or Semiconductor-relatedfields ? Strong understanding of semiconductor devices and materials (FinFET,GAA, HKMG preferred) ? Familiarity with device characterization techniques(e.g., MOSCAP, CV measurement) is a plus ? Ability to analyze technicalliterature and patents independently ? Strong analytical thinking andstructured communication skills ? Good English reading and writing skills________________________________________ Nice to Have ? Exposure tohigh-k/metal gate integration or materials research ? Experience with failureanalysis or DFMEA methodologies