Graduate_Circuit Design Engineer

招聘部门：PDG 【职位介绍】 1. Arm China PDG group design and support physical IP on Chinese foundry partners and offers IC designers a wide range of choices from its broad portfolio of Arm China owned physical IP. Arm China PDG group physical IP include high-performance, high-density, low-power and ultra-low power Logic IP, Embedded Memory Compiler and Interface IP for each foundry and process technology. These productions ease implementation challenges for advanced nodes to accelerate core hardening, speed SoC implementation and reduce project rise for IC design. 2. 安谋科技 PDG（物理IP设计团队）致力于在中国本土晶圆厂合作伙伴的工艺上设计、开发并支持物理 IP，并凭借安谋科技自有的广泛物理 IP 产品组合，为客户提供丰富多样的选择。安谋科技 PDG 团队的物理 IP 产品涵盖了高性能、高密度、低功耗及超低功耗逻辑 IP、嵌入式存储器编译器（Embedded Memory Compiler）等。这些产品能够缓解先进工艺节点的设计实现挑战，从而加速内核硬化（Core Hardening）进程、提升 SoC 整体实现效率，并降低 IC 设计项目的整体风险。 【职位职责】 1. Responsible for the development of physical IP (standard cell library, memory and IO) structure definition and circuit design on different process technology. 2. 负责不同工艺节点下物理 IP（标准单元库、存储器及 IO）的架构定义与电路设计； 3. Responsible for physical IP development flow and design methodology. 4. 负责物理 IP 的开发流程与整体设计方法论； 5. Analyze and optimize physical IP timing, power and area. 6. 对物理 IP 的时序、功耗及面积（PPA）进行分析与优化； 7. Guide layout engineer, assist in layout optimization based on post-simulation results. 8. 指导版图工程师，基于后仿真结果协助进行版图优化。 【任职要求】 1. Master degree or above in related fields such electrical engineering, computer science, physics etc. 2. 硕士及以上学历，电子工程、计算机科学、物理等相关专业背景； 3. Good understanding semiconductor process/devices/physics, familiar with transistor lever circuit simulation and verification. 4. 具备扎实的半导体工艺/器件/物理基础，熟悉晶体管级电路仿真与验证； 5. Skillful in the use of EDA tools (virtuoso, spectre, hspice, HSIM, Finesim, StarRC etc.). 6. 熟练使用各类 EDA 工具（如 Virtuoso, Spectre, HSPICE, HSIM, Finesim, StarRC 等）； 7. Familiar with ASIC back-end flow (from RTL TO GDS): synthesis, STA, formal verification, CTS, place and route. 8. 熟悉 ASIC 【学历要求】 硕士及以上 【硬性专业要求】 电子工程相关专业、计算机科学相关专业、物理相关专业