Graduate_SOC Design Engineer

招聘部门：ASIC Service BU 【职位职责】 1. Module Design & Integration: Responsible for RTL coding (Verilog/SystemVerilog) and integration of subsystems/functional modules (e.g., buses, peripheral interfaces, control logic) in SoC chips. 2. 模块设计与集成：负责 SoC 芯片中子系统及功能模块（如总线、外设接口、控制逻辑等）的 RTL 代码编写（Verilog/SystemVerilog）与集成。 3. Front-End Simulation & Debug: Work closely with the verification team to conduct block-level and top-level functional simulation, debugging, and bug tracking. 4. 前仿真与设计查错：配合验证团队完成模块级（Block-level）和芯片级（Top-level）的功能仿真、调试与 Bug 定位。 5. Design Quality Control: Perform Lint, CDC (Cross-Clock Domain) checks, and sanity checks prior to FPGA prototyping to ensure compliance with industry design standards. 6. 设计质量把控：运行 lint、CDC（跨时钟域）检查以及 FPGA 原型验证前的质量把控，确保设计规范符合工业标准。 7. Logic Synthesis & Timing Analysis: Assist in logic synthesis, Static Timing Analysis (STA), and low-power design optimization (UPF). 8. 逻辑综合与时序分析：协助完成逻辑综合（Synthesis）、静态时序分析（STA）及功耗优化（UPF/Low-Power Design）。 9. Documentation: Draft comprehensive Design Specifications, interface definitions, and register maps. 10. 文档撰写：撰写详细的设计规格文档（Design Spec）、接口定义和寄存器手册。 【任职要求】 1. Master’s degree or above in Microelectronics, Integrated Circuit Design, Electronic Engineering, Computer Science, or related fields (Outstanding Bachelor's candidates will also be considered). 2. 微电子、集成电路、电子工程、计算机科学或相关专业，硕士及以上学历（优秀本科生亦可）。 3. Deep understanding of digital logic design principles, computer architecture, and basic SoC/CPU concepts. 4. 深入理解数字电子技术原理、计算机体系结构与 CPU/SoC 基本架构。 5. Proficient in Verilog / SystemVerilog HDL with good RTL coding habits. 6. 熟练掌握 Verilog / SystemVerilog 硬件描述语言，具备良好的 RTL 编码习惯。 7. Solid understanding of digital timing concepts (e.g., Setup/Hold time, Clock Domain Crossing, etc.). 8. 掌握基本的数字电路时序概念（如 Setup/Hold Time、Clock Domain Crossing 等）。 9. Familiar with mainstream EDA simulation and design tools (e.g., VCS, Design Compiler, SpyGlass). 10. 熟悉常见的 EDA 仿真与设计 【学历要求】 硕士及以上 【硬性专业要求】 微电子相关专业、集成电路相关专业、电子工程相关专业、计算机科学相关专业