芯原微电子(上海)股份有限公司

职位名称：硬件测试工程师 职位描述： 1. 负责FPGA/EMU工程日常维护、代码更新、综合编译、比特流生成； 2.负责FPGA/EMU系统功能测试、回归测试，保障版本质量稳定； 3.基于Python独立编写和维护自动化测试脚本，实现测试报告自动化输出，持续提升团队测试效率； 4.负责测试数据汇总、测试报告输出，针对编译报错、功能故障、板级问题进行分析定位； 5. 配合软硬件、算法团队完成联合调试，支撑产品稳定交付； 6.负责客户侧技术答疑、测试进度同步、问题反馈、交付跟进与技术诉求闭环。 职位要求： 1. 本科及以上学历，微电子、通信工程、自动化、计算机等相关专业； 2.掌握Verilog基础语法，熟悉FPGA开发基本流程，熟练使用Vivado编译工具； 3.具备扎实的Python脚本开发能力，有自动化测试、日志解析、批量处理、自动化报告生成相关经验； 4. 有AIAgent工具应用、流程智能化落地相关经验者优先； 5. 性格沉稳、心理素质良好、抗压能力强，沟通表达清晰、服务意识强，适应对外技术沟通场景； 6.富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：海口 Title: Hardware Release QualificationEngineer Responsibilities: 1. Responsible for the daily maintenance, codeupdates, synthesis, compilation, and bitstream generation of FPGA/EMU projects.2. Conduct system functional testing and regression testing for FPGA/EMU toensure stable version quality. 3. Independently develop and maintain automatedtest scripts using Python, realize automatic generation of test reports, andcontinuously improve team testing efficiency. 4. Collect and summarize testdata, deliver test reports, and analyze and locate compilation errors,functional failures, and board-level problems. 5. Collaborate with software,hardware and algorithm teams on joint debugging to support stable productdelivery. 6. Responsible for technical Q&A, test progress synchronization,problem feedback, delivery follow-up, and closed-loop management of customertechnical requirements. Requirements: 1. Bachelor's degree or above, majoringin Microelectronics, Communications Engineering, Automation, Computer Scienceor related fields. 2. Proficient in basic Verilog syntax, familiar with theoverall FPGA development process, and experienced in using Vivado compilationtools. 3. Solid Python scripting development capabilities, with practicalexperience in automated testing, log parsing, batch data processing andautomatic report generation. 4. Candidates with experience in AI Agent toolapplication and intelligent process implementation are preferred. 5. Calmpersonality, good psychological quality and strong pressure resistance. Possessclear communication skills and strong service awareness; capable of externalcommunication work. 6. Self-motivated and a good team player. Goodcommunication skills in both Chinese and English in either listening, speaking,reading or writing. Location: Haikou

职位名称：基础IP电路设计工程师 职位描述： 1.设计开发基于CMOS深亚微米及纳米级工艺的基础IP电路，包含标准单元、存储器和用于优化芯片性能功耗面积的定制电路； 2.指导版图设计，并基于后仿真结果协助其优化版图； 3. 库的特征化以及产生数字设计流程所需的设计模型，包含Synopsys libertymodel、Verilog等； 4. 设计标准单元/存储器的电路测试芯片，并协助测试工程师进行测试。 职位要求： 1. 电子工程等相关专业硕士及以上学历；2. 掌握电路设计及器件物理知识，有相关标准单元或存储器电路设计经验优先； 3. 熟悉相关的EDA工具及脚本语言，了解Linux基础知识； 4.有相关AI辅助设计及机器学习在IC设计中应用经验者优先； 5. 富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：海口 Title:Foundation IP Circuit Design Engineer Responsibilities: 1. Design and developfoundation IP circuits based on CMOS deep sub-micron and nanometer scaleprocesses, including standard cells, memories and custom circuits foroptimizing chip performance, power consumption and area. 2. Guide layoutdesigner, assist in layout optimization based on post-layout simulationresults. 3. Characterize libraries and generate design models supporting majorEDA design flows, including Synopsys liberty model, Verilog, etc. 4. Designtest chips for STD/MEM libraries and assist in testing. Requirements: 1.Master's or above degree in EE or related majors. 2. Strong knowledge ofcircuit design and device physics, experience with standard cells or memorycircuits is preferred. 3. Basic knowledge and skills of Linux, script languageand EDA tools. 4. Experience with AI/ML-assisted circuit design tools is aplus. 5. Self-motivated and a good team player. Good communication skills inboth Chinese and English in either listening, speaking, reading or writing.Location: Haikou

职位名称：版图设计工程师 职位描述： 1. 合作完成基于业界先进的CMOSFinfet/FDSOI以及特色成熟工艺下的基础IP库，模拟及混合信号IP，无线射频IP，ASIC定制芯片等的版图正向开发； 2.完成DRC/LVS/DFM等sign-off物理验证，寄生参数的抽取及设计优化； 3. 根据公司设计流程产生流片数据包。 职位要求： 1.微电子/电子工程/物理电子等相关专业本科及以上学历； 2. 扎实掌握半导体器件，制造工艺，模拟电路原理等相关基础知识； 3. 符合以下条件者优先： 硕士学历；熟悉Unix/Linux系统，Cadence/Mentor IC开发工具及流程； Perl/Tcl/Skill脚本编程基础； 4.有相关AI辅助设计及机器学习在IC设计中应用经验者优先； 5. 富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：海口 Title:Layout Design Engineer Responsibilities: 1. Collaborate on layout design offoundation IP library, Analog and Mix-signal IP, Wireless RF IP and ASIC chipsbased on the most advanced CMOS Finfet/FDSOI and specialized mature processes.2. Finish sign-off verification (DRC/LVS/DFM…), parasitic extraction, andlayout optimization. 3. Generate IP tape-out kits following design flow.Requirements: 1. Bachelor's or above degree in Microelectronics, EE, PhysicalElectronics or related majors. 2. Solid understanding of semiconductor devices,IC manufacturing, and analog circuit principles. 3. Candidates meeting thefollowing criteria are preferred: Master's degree. Be familiar with Unix/LinuxOS, experiences in Cadence/Mentor EDA tools and flow. scripting skills(Perl/Tcl/Skill). 4. Experience in AI-assisted design and ML applications forIC design is a plus. 5. Self-motivated and a good team player. Goodcommunication skills in both Chinese and English in either listening, speaking,reading or writing. Location: Haikou

职位名称：数字前端设计/验证工程师 职位描述： 1. 独立完成ASIC功能模块的设计任务，包括：需求分析，架构定义，模块设计，逻辑综合和时序分析； 2.独立完成ASIC功能模块的验证任务，包括：制定验证方案，搭建测试环境，编写测试用例等； 3. 负责芯片顶层及子模块的逻辑综合和时序分析；以及相关DFTRTL代码编写，扫描链，MBIST电路，边界扫描电路插入，以及测试pattern的生成及仿真等； 4.作为芯片的设计者，配合系统工程师、物理实现工程师和测试工程师，解决功能验证、平面布置图设计、时序优化/收敛、可测试设计和芯片测试方面的问题。 职位要求： 1.硕士及以上学历，电子工程或计算机科学相关专业； 2. 熟悉RTL Coding/UVM（Verilog/SystemVerilog）； 3.熟悉ASIC的设计流程，特别是从规格文档到架构定义，再到RTL实现、验证和综合； 4.熟练应用EDA工具（Synopsys或Cadence）：VCS、Xcelium、DC、PT等； 5. 熟悉C/C++语言、Perl、Python等脚本语言；6. 熟悉SOC片上总线协议如AMBA、NOC的优先； 7. 有ARM、RISC-V、GPU、DSP、VPU、NPU、ISP、DisplayIP等处理器设计背景优先； 8. 有USB、PCIe、CXL、UCIe、Ethernet、DDR、UFS、DP等接口背景的优先； 9.有相关AI辅助设计及机器学习在IC设计中应用经验者优先； 10. 富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：上海/成都/南京/广州Title: ASIC Design/Verification Engineer Responsibilities: 1. Independentlywork on the design of ASIC functional blocks in terms of requirement analysis,architecture definition, block design, logic synthesis, and timing analysis(STA). 2. Independently work on the verification of ASIC functional blocks interms of verification plan, test bench building up, test case development, andother related tasks. 3. Perform logic synthesis and timing analysis of chipsand sub-blocks, as well as DFT RTL coding, scan chain/MBIST/boundary scancircuits insertion, and test pattern generation and simulation. 4. Work closelywith system engineers, physical implementation designers, and testing engineersto complete functional verification, floorplan design, timingoptimization/closure, and DFT & ATE testing. Requirements: 1. Master's or abovedegree in EE/CS related majors. 2. Familiar with RTL coding/UVM(Verilog/SystemVerilog). 3. Familiar with the ASIC design flow, includingspecification, architecture definition, RTL coding, verification, andsynthesis. 4. Adept at EDA tools (Synopsys or Cadence), such as VCS, Xcelium,DC, PT. 5. Familiar with C/C++, Perl, Python, or other programming language. 6.A knowledge of SOC on-chip bus protocols (AMBA/NOC) is a plus. 7. A knowledgeof processor design (ARM, RISC-V, GPU, DSP, VPU, NPU, ISP, Display IP) is aplus. 8. A knowledge of interfaces such asUSB/PCIe/CXL/UCIe/Ethernet/DDR/UFS/DP is a plus. 9. Experience in AI-assisteddesign and ML applications in IC design is a plus. 10. Self-motivated and agood team player. Good communication skills in both Chinese and English ineither listening, speaking, reading or writing. Location:Shanghai/Chengdu/Nanjing/Guangzhou

职位名称：数字前端设计/验证工程师 职位描述： 1. 独立完成ASIC功能模块的设计任务，包括：需求分析，架构定义，模块设计，逻辑综合和时序分析； 2.独立完成ASIC功能模块的验证任务，包括：制定验证方案，搭建测试环境，编写测试用例等； 3. 负责芯片顶层及子模块的逻辑综合和时序分析；以及相关DFTRTL代码编写，扫描链，MBIST电路，边界扫描电路插入，以及测试pattern的生成及仿真等； 4.作为芯片的设计者，配合系统工程师、物理实现工程师和测试工程师，解决功能验证、平面布置图设计、时序优化/收敛、可测试设计和芯片测试方面的问题。 职位要求： 1.硕士及以上学历，电子工程或计算机科学相关专业； 2. 熟悉RTL Coding/UVM（Verilog/SystemVerilog）； 3.熟悉ASIC的设计流程，特别是从规格文档到架构定义，再到RTL实现、验证和综合； 4.熟练应用EDA工具（Synopsys或Cadence）：VCS、Xcelium、DC、PT等； 5. 熟悉C/C++语言、Perl、Python等脚本语言；6. 熟悉SOC片上总线协议如AMBA、NOC的优先； 7. 有ARM、RISC-V、GPU、DSP、VPU、NPU、ISP、DisplayIP等处理器设计背景优先； 8. 有USB、PCIe、CXL、UCIe、Ethernet、DDR、UFS、DP等接口背景的优先； 9.有相关AI辅助设计及机器学习在IC设计中应用经验者优先； 10. 富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：上海/成都/南京/广州Title: ASIC Design/Verification Engineer Responsibilities: 1. Independentlywork on the design of ASIC functional blocks in terms of requirement analysis,architecture definition, block design, logic synthesis, and timing analysis(STA). 2. Independently work on the verification of ASIC functional blocks interms of verification plan, test bench building up, test case development, andother related tasks. 3. Perform logic synthesis and timing analysis of chipsand sub-blocks, as well as DFT RTL coding, scan chain/MBIST/boundary scancircuits insertion, and test pattern generation and simulation. 4. Work closelywith system engineers, physical implementation designers, and testing engineersto complete functional verification, floorplan design, timingoptimization/closure, and DFT & ATE testing. Requirements: 1. Master's or abovedegree in EE/CS related majors. 2. Familiar with RTL coding/UVM(Verilog/SystemVerilog). 3. Familiar with the ASIC design flow, includingspecification, architecture definition, RTL coding, verification, andsynthesis. 4. Adept at EDA tools (Synopsys or Cadence), such as VCS, Xcelium,DC, PT. 5. Familiar with C/C++, Perl, Python, or other programming language. 6.A knowledge of SOC on-chip bus protocols (AMBA/NOC) is a plus. 7. A knowledgeof processor design (ARM, RISC-V, GPU, DSP, VPU, NPU, ISP, Display IP) is aplus. 8. A knowledge of interfaces such asUSB/PCIe/CXL/UCIe/Ethernet/DDR/UFS/DP is a plus. 9. Experience in AI-assisteddesign and ML applications in IC design is a plus. 10. Self-motivated and agood team player. Good communication skills in both Chinese and English ineither listening, speaking, reading or writing. Location:Shanghai/Chengdu/Nanjing/Guangzhou

职位名称：软件工程师 职位描述： 根据个人情况及公司发展规划，承担如下职责之一： 1.负责GPU/GPGPU/NPU/VPU/ISP/ZSP/DPU/Security IP/Interface IP/CommunicationIP的软件设计、开发和优化工作； 2. 负责各种IP C模型的建模工作； 3.负责上层AI软件框架的适配及开发工作，提升AI模型在GPU/GPGPU/NPU处理器上的性能； 4.参与Windows/Android/Linux/Chromium/嵌入式SDK的软件测试与自动化等工作。 职位要求： 满足两种或以上条件者优先考虑： 1.计算机、通信工程、信息工程、电子工程、自动化等相关专业本科及以上学历； 2. 熟悉或精通一门编程语言，具体语言不限，熟悉C/C++，Python等； 3.对操作系统和数据结构有良好的理解； 4. 清楚了解硬件、软件交互和系统级性能分析；了解Linux内核驱动或Windows WDDM驱动开发； 5.理解一种或者一种以上操作系统，有过实际项目开发经验的优先； 6. 熟悉GPU/GPGPU/NPU/VPU/ISP/ZSP/DPU/SecurityIP/Interface IP/Communication IP并有实际项目的开发经验优先； 7.熟悉诸如PyTorch和ONNX框架且对GPU/GPGPU/NPU上AI算子开发经验者优先； 8. 熟悉MLIR/TVM/Triton等AI编译器框架者优先；9. 熟悉DX/OpenGL/Vulkan/OpenCL/CUDA者优先； 10. 熟练使用AI，善于使用AI进行开发； 11.富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：成都/南京 Title: Software EngineerResponsibilities: You will be in a position responsible for one of thefollowing assignments: 1. Design, develop and optimize software forGPU/GPGPU/NPU/VPU/ISP/ZSP/DPU/Security IP/Interface IP/Communication IP. 2.Design and develop C-model for different IP processors. 3. Develop VSIproprietary software code to adapt upper-level AI frameworks and enhance theperformance of AI models on GPU/GPGPU/NPU IP processors. 4. Develop devicedrivers and software based on Windows/Android/Linux/Chromium/ FreeRTOS, etc.Conduct automation testing. Requirements: Candidates meet two or above twocriteria are preferred: 1. Major in Computer Science, CommunicationsEngineering, Information Engineering, Electronic Engineering and Automation,etc. with B.S degree or above. 2. Experienced with programming at least withone programming language, C/C++, Python or assembly is even better. 3. A goodunderstanding of operating systems and data structures. 4. Understandhardware/software interaction and system-level tradeoffs; understand Linuxkernel driver development or Windows WDDM driver development. 5. Knowledge ofat least one operating system, with real programming project experience is aplus. 6. Knowledge of GPU/GPGPU/NPU/VPU/ISP/ZSP/DPU/Security IP/InterfaceIP/Communication IP, with real project experience is a plus. 7. Familiaritywith AI frameworks (such as PyTorch and ONNX) and development of AI computingoperators on GPU/GPGPU/NPU is a plus. 8. Familiarity with AI Compiler such asMLIR, TVM and Triton is a plus. 9. Familiarity withDX/OpenGL/Vulkan/OpenCL/CUDA is a plus. 10. Proficient in AI utilization andskilled in AI-driven development. 11. Self-motivated and a good team player.Good communication skills in both Chinese and English in either listening,speaking, reading or writing. Location: Chengdu/Nanjing

职位名称：射频集成电路设计工程师 职位描述： 1. 设计CMOS/FDSOI无线IC芯片的射频模拟电路； 2. 指导、监督高质量版图设计； 3.协助设计测试板，调试测试芯片，根据测试结果迭代改进方案。 职位要求： 1. 电子或微电子专业硕士/博士学历； 2. 扎实的相关课程知识及项目经验； 3.有以下设计经验优先： 射频transceiver电路，如BLE、WIFI、NBIoT、GNSS；PA、LNA、MIXER、PLL、VCO、Filter、VGA/PGA、AD/DA、Low Power PMU、XO等； 4.有测试仪器使用经验，如示波器、频谱分析仪、信号源等； 5. 能够熟练使用AI工具辅助研发工作； 6. 富有事业心和团队合作精神，良好的中英文听说读写能力。工作地点：成都/南京 Title: RFIC Design Engineer Responsibilities: 1. Design RF Analogfront-end circuits based on CMOS/FDSOI technology for wireless IC chips. 2.Guide and/or supervise layout designers for high-quality layout. 3. Assist intest board design, debug and verify test chips, and iterate design based on thetest results to optimize the function and performance. Requirements: 1.Master's or PhD degree in EE or Micro-Electronics. 2. Solid course knowledgeand project experience in related areas. 3. Experience in design of thefollowing circuits is preferred: RF transceiver systems: BLE, WIFI, NBIoT,GNSS, etc. PA, LNA, MIXER, PLL, VCO, Filter, VGA/PGA, AD/DA, Low Power PMU, XO,etc. 4. Capability to operate test instruments, including oscilloscope,spectrum analyzer, and signal generator. 5. Experience in AI-assisted tools forIC design is a plus. 6. Self-motivated and a good team player. Goodcommunication skills in both Chinese and English in either listening, speaking,reading or writing. Location: Chengdu/Nanjing

职位名称：数字后端设计工程师 职位描述： 根据个人情况和公司项目规划，承担如下一种或多种职责： 1.完成编写时序约束，编写低功耗设计文件（UPF/CPF），逻辑综合/物理综合，形式验证，静态时序分析，功耗分析，低功耗设计规则检查（CLP）； 2.完成布局规划，电源规划，布图布线，物理验证，电压降分析，电迁移分析； 3.完成DFT逻辑设计和验证，完成编写DFT模式时序约束，帮助DFT模式时序收敛，帮助芯片bring-up，完成测试向量的调试，良率的提升； 4.探索并引入AI/ML辅助EDA工具（如智能时序预测、自动布局优化、功耗智能调优等），提升后端设计流程的效率与结果质量； 5.参与或主导基于机器学习的数据分析项目，辅助参数预测、异常检测或时序建模等； 6. 为客户/现场应用工程师/销售人员提供技术支持。 职位要求： 1.电子工程硕士或更高学历； 2. 具备以下单项或多项经验：从RTL到GDS的设计实现，芯片级测试，ASIC编码和模拟，ASIC物理版图，集成电路制造和工艺；3. 对人工智能/机器学习在芯片设计中的应用有兴趣或实践经验（如使用过ML工具包、了解时序/功耗预测模型、自动化脚本优化等）； 4.具备基础的数据处理和编程能力 （如Python/Tcl/Perl）， 能够利用AI框架 （如TensorFlow/PyTorch）进行简单的模型训练或推理；5. 能够熟练使用AI工具辅助研发工作者优先； 6. 富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：上海/成都/南京 Title:Physical Design Engineer Responsibilities: You will be in a positionresponsible for one or more of below assignments: 1. Complete writing timingconstraint, writing UPF/CPF, logic/physical synthesis, formal verification,STA, power analysis, CLP. 2. Complete floorplan, power plan, P&R, physicalverification, IRDrop analysis, EM analysis. 3. Complete DFT logic design andverification, writing DFT mode timing constraint, support DFT mode timingclosure, support chip bring-up, complete test pattern debugging and yieldimprovement. 4. Explore and introduce AI/ML assisted EDA tools (e.g.,intelligent timing prediction, automated placement optimization, smart powertuning) to improve the efficiency and quality of the physical design flow. 5.Participate in or lead machine learning based data analytics projects tosupport parameter prediction, anomaly detection, and timing modeling, amongothers. 6. Provide technical support for customer/FAE/sales. Requirements: 1.Master's or above degree in EE. 2. Have following single or multipleexperiences: design implementation from RTL to GDS, chip level testing, ASICcoding and simulation, ASIC physical layout, IC manufacture and process. 3.Interest or hands-on experience in applying AI/ML to chip design (e.g., usingML toolkits, understanding timing/power prediction models, automated scriptoptimization). 4. Basic data processing and programming skills (e.g.,Python/Tcl/Perl), with the ability to use AI frameworks (e.g.,TensorFlow/PyTorch) for simple model training or inference. 5. Familiarity withAI tools applied in R&D is preferred. 6. Self-motivated and a good team player.Good communication skills in both Chinese and English in either listening,speaking, reading or writing. Location: Shanghai/Chengdu/Nanjing

职位名称：算法工程师 职位描述： 根据个人情况和公司项目规划，承担如下一种或多种职责： 1. 开发优化射频及数字前端DFE算法模型及其定点软硬件实现； 2.开发图像类传统及AI算法（降噪/去马赛克/HDR/压缩/插帧/3D），并优化部署于自研硬件平台； 3. 优化算法，完成算法在实际的解决方案中的集成以及实施；4. 为硬件、软件、客户提供所需的测试用例； 5. 推动算法从原型到硬件实现，含模型开发优化、硬件友好设计、RTL协同及验证支持； 6.能够熟练使用AI工具辅助研发工作。 职位要求： 1. 计算机科学与技术、软件工程、通信工程、信息工程、电子工程、生物医学工程等相关专业硕士优先； 2.熟悉C/C++、Matlab等编程语言； 3. 有一个或多个相关领域算法开发经验的优先，如：LTE、BT/BLE、Wi-Fi或GNSS导航，射频收发机校准和预失真，数字图像处理与内容识别，图像/视频压缩等；DSP（数字信号处理器）、ISP（图像信号处理器）、DPU（显示领域图像信号处理器）、健康算法等相关课题或实习经验； 4.熟悉深度学习框架，有图像/视频增强算法经验，了解模型量化与端侧部署者优先； 5. 有算法硬件协同设计经验的优先； 6.富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：上海/成都/南京 Title: Algorithm EngineerResponsibilities: You will be in a position responsible for one or more ofbelow assignments: 1. Develop and optimize RF and digital front-end (DFE)algorithm models, along with their fixed-point software/hardwareimplementation. 2. Develop image-related AI algorithms (denoising,depigmentation, HDR, compression, frame generation, 3D) and optimize theirdeployment on self-developed hardware platforms. 3. Optimize algorithms,integrating and applying the algorithms to real projects. 4. Develop therelated test cases to support hardware, software and customers as needed. 5.Drive algorithm development from prototype design to hardware implementation,including algorithm model development and optimization, hardware-friendlydesign, RTL/architecture collaboration, and verification support. 6. Beproficient in using AI tools to assist in R&D work. Requirements: 1. Master'sdegree in Computer Science, Software Engineering, Communications Engineering,Information Engineering, Electronic Engineering, Biomedical Engineering orrelated majors is preferred. 2. Familiar with programming languages such asC/C++ and Matlab. 3. Algorithm development experience in related fields is aplus: LTE, BT/BLE, Wi-Fi or GNSS, RF transceiver calibration, pre-distortion,digital image processing/content recognition and image/video compression. DSP(digital signal processor), ISP (Image Signal Processor), DPU (Display ProcessUnit)，health algorithm, etc. 4. Familiarity with deep learning frameworks,experience with image/video enhancement algorithms, and understanding of modelquantization and edge deployment are preferred. 5. Experience inalgorithm-hardware co-design is preferred. 6. Self-motivated and a good teamplayer. Good communication skills in both Chinese and English in eitherlistening, speaking, reading or writing. Location: Shanghai/Chengdu/Nanjing

职位名称：数字后端设计工程师 职位描述： 根据个人情况和公司项目规划，承担如下一种或多种职责： 1.完成编写时序约束，编写低功耗设计文件（UPF/CPF），逻辑综合/物理综合，形式验证，静态时序分析，功耗分析，低功耗设计规则检查（CLP）； 2.完成布局规划，电源规划，布图布线，物理验证，电压降分析，电迁移分析； 3.完成DFT逻辑设计和验证，完成编写DFT模式时序约束，帮助DFT模式时序收敛，帮助芯片bring-up，完成测试向量的调试，良率的提升； 4.探索并引入AI/ML辅助EDA工具（如智能时序预测、自动布局优化、功耗智能调优等），提升后端设计流程的效率与结果质量； 5.参与或主导基于机器学习的数据分析项目，辅助参数预测、异常检测或时序建模等； 6. 为客户/现场应用工程师/销售人员提供技术支持。 职位要求： 1.电子工程硕士或更高学历； 2. 具备以下单项或多项经验：从RTL到GDS的设计实现，芯片级测试，ASIC编码和模拟，ASIC物理版图，集成电路制造和工艺；3. 对人工智能/机器学习在芯片设计中的应用有兴趣或实践经验（如使用过ML工具包、了解时序/功耗预测模型、自动化脚本优化等）； 4.具备基础的数据处理和编程能力 （如Python/Tcl/Perl）， 能够利用AI框架 （如TensorFlow/PyTorch）进行简单的模型训练或推理；5. 能够熟练使用AI工具辅助研发工作者优先； 6. 富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：上海/成都/南京 Title:Physical Design Engineer Responsibilities: You will be in a positionresponsible for one or more of below assignments: 1. Complete writing timingconstraint, writing UPF/CPF, logic/physical synthesis, formal verification,STA, power analysis, CLP. 2. Complete floorplan, power plan, P&R, physicalverification, IRDrop analysis, EM analysis. 3. Complete DFT logic design andverification, writing DFT mode timing constraint, support DFT mode timingclosure, support chip bring-up, complete test pattern debugging and yieldimprovement. 4. Explore and introduce AI/ML assisted EDA tools (e.g.,intelligent timing prediction, automated placement optimization, smart powertuning) to improve the efficiency and quality of the physical design flow. 5.Participate in or lead machine learning based data analytics projects tosupport parameter prediction, anomaly detection, and timing modeling, amongothers. 6. Provide technical support for customer/FAE/sales. Requirements: 1.Master's or above degree in EE. 2. Have following single or multipleexperiences: design implementation from RTL to GDS, chip level testing, ASICcoding and simulation, ASIC physical layout, IC manufacture and process. 3.Interest or hands-on experience in applying AI/ML to chip design (e.g., usingML toolkits, understanding timing/power prediction models, automated scriptoptimization). 4. Basic data processing and programming skills (e.g.,Python/Tcl/Perl), with the ability to use AI frameworks (e.g.,TensorFlow/PyTorch) for simple model training or inference. 5. Familiarity withAI tools applied in R&D is preferred. 6. Self-motivated and a good team player.Good communication skills in both Chinese and English in either listening,speaking, reading or writing. Location: Shanghai/Chengdu/Nanjing

职位名称：编译器工程师 职位描述： 1. 负责为Verisilicon的(GP)GPU等IP设计、开发和维护前端和后端编译器，参与AI编译器的建设； 2.分析编译器所产生代码，提出编译器优化方案； 3. 与硬件和架构部门、系统软件部门密切合作，理解硬件和软件的需求，从编译器角度参与硬件和软件系统的设计。职位要求： 1. 硕士及以上学历，计算机相关专业； 2. 扎实的C/C++编程能力和数据结构和算法知识； 3. 优秀的线性代数知识； 4.有编译器开发经验者优先考虑； 5. 对LLVM和GCC熟悉者优先考虑； 6. 熟悉CPU/(GP)GPU等体系结构者优先考虑； 7. 熟练使用AI者优先；8. 富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：上海/成都 Title: Compiler EngineerResponsibilities: 1. Design, develop and maintain front-end and back-endcompilers for (GP)GPU or other IPs, as well as AI compilers. 2. Analyze thecompiler-generated codes and provide solutions to optimizing compilers. 3. Workclosely with hardware, architecture and software teams to clarify hardware andsoftware requirements. Participate in hardware and software design from thecompiler's perspective. Requirements: 1. Master's or above degree in CS relatedmajors. 2. Strong C/C++ programming skill and solid knowledge of data structureand algorithm. 3. Excellent knowledge of linear algebra. 4. Experience incompiler development is a plus. 5. Familiarity with LLVM/GCC is a plus. 6.Familiarity with CPU/(GP)GPU architecture is a plus. 7. Proficiency in AI is aplus. 8. Self-motivated and a good team player. Good communication skills inboth Chinese and English in either listening, speaking, reading or writing.Location: Shanghai/Chengdu

职位名称：算法工程师 职位描述： 根据个人情况和公司项目规划，承担如下一种或多种职责： 1. 开发优化射频及数字前端DFE算法模型及其定点软硬件实现； 2.开发图像类传统及AI算法（降噪/去马赛克/HDR/压缩/插帧/3D），并优化部署于自研硬件平台； 3. 优化算法，完成算法在实际的解决方案中的集成以及实施；4. 为硬件、软件、客户提供所需的测试用例； 5. 推动算法从原型到硬件实现，含模型开发优化、硬件友好设计、RTL协同及验证支持； 6.能够熟练使用AI工具辅助研发工作。 职位要求： 1. 计算机科学与技术、软件工程、通信工程、信息工程、电子工程、生物医学工程等相关专业硕士优先； 2.熟悉C/C++、Matlab等编程语言； 3. 有一个或多个相关领域算法开发经验的优先，如：LTE、BT/BLE、Wi-Fi或GNSS导航，射频收发机校准和预失真，数字图像处理与内容识别，图像/视频压缩等；DSP（数字信号处理器）、ISP（图像信号处理器）、DPU（显示领域图像信号处理器）、健康算法等相关课题或实习经验； 4.熟悉深度学习框架，有图像/视频增强算法经验，了解模型量化与端侧部署者优先； 5. 有算法硬件协同设计经验的优先； 6.富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：上海/成都/南京 Title: Algorithm EngineerResponsibilities: You will be in a position responsible for one or more ofbelow assignments: 1. Develop and optimize RF and digital front-end (DFE)algorithm models, along with their fixed-point software/hardwareimplementation. 2. Develop image-related AI algorithms (denoising,depigmentation, HDR, compression, frame generation, 3D) and optimize theirdeployment on self-developed hardware platforms. 3. Optimize algorithms,integrating and applying the algorithms to real projects. 4. Develop therelated test cases to support hardware, software and customers as needed. 5.Drive algorithm development from prototype design to hardware implementation,including algorithm model development and optimization, hardware-friendlydesign, RTL/architecture collaboration, and verification support. 6. Beproficient in using AI tools to assist in R&D work. Requirements: 1. Master'sdegree in Computer Science, Software Engineering, Communications Engineering,Information Engineering, Electronic Engineering, Biomedical Engineering orrelated majors is preferred. 2. Familiar with programming languages such asC/C++ and Matlab. 3. Algorithm development experience in related fields is aplus: LTE, BT/BLE, Wi-Fi or GNSS, RF transceiver calibration, pre-distortion,digital image processing/content recognition and image/video compression. DSP(digital signal processor), ISP (Image Signal Processor), DPU (Display ProcessUnit)，health algorithm, etc. 4. Familiarity with deep learning frameworks,experience with image/video enhancement algorithms, and understanding of modelquantization and edge deployment are preferred. 5. Experience inalgorithm-hardware co-design is preferred. 6. Self-motivated and a good teamplayer. Good communication skills in both Chinese and English in eitherlistening, speaking, reading or writing. Location: Shanghai/Chengdu/Nanjing

职位名称：架构工程师 职位描述： 1. 对GPU/GPGPU/NPU处理器进行相应的算法/架构（C-Model或PerformanceModel）设计与开发； 2. 开发测试计划/测试实例/测试架构进行功能和性能分析； 3.帮助硬件工程师定义硬件架构，进行模块级和整个IP的设计和验证，优化架构设计； 4. 配合驱动和编译器团队在产品级软件平台上的验证和性能分析和调优。 职位要求：1. 硕士及以上学历，计算机/电子工程等相关专业； 2. 熟悉C/C++编程，有一定脚本编程能力； 3.有计算机体系结构/计算机图形学/HPC/AI算法/System C编程/Verilog项目经验者优先； 4. 在硬件设计开发及优化方面有了解； 5.熟练使用AI者优先； 6. 富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：上海/成都 Title: ArchitectureEngineer Responsibilities: 1. Design and implement algorithm/architecture(C-Models/Performance Model) for GPU, GPGPU and NPU. 2. Develop test plans,test examples and test infrastructure to verify functionality and performance.3. Support hardware engineers to define the hardware architecture and help themin design, validation and debugging at both module level and top level tooptimize the architecture. 4. On production level software stack, for givenprocessor architecture, co-work with driver and compiler teams to verifyfunctionality and analyze/tune performance. Requirements: 1. Master's or abovedegree in CS/EE or related majors. 2. Strong programming skills in C/C++.Knowledge of script programming. 3. Experience in computer architecture,computer graphics, HPC, AI algorithm, System C or Verilog is a plus. 4.Familiarity with hardware design and optimization is a plus. 5. Proficiency inAI is a plus. 6. Self-motivated and a good team player. Good communicationskills in both Chinese and English in either listening, speaking, reading orwriting. Location: Shanghai/Chengdu

职位名称：数字前端设计/验证工程师 职位描述： 1. 独立完成ASIC功能模块的设计任务，包括：需求分析，架构定义，模块设计，逻辑综合和时序分析； 2.独立完成ASIC功能模块的验证任务，包括：制定验证方案，搭建测试环境，编写测试用例等； 3. 负责芯片顶层及子模块的逻辑综合和时序分析；以及相关DFTRTL代码编写，扫描链，MBIST电路，边界扫描电路插入，以及测试pattern的生成及仿真等； 4.作为芯片的设计者，配合系统工程师、物理实现工程师和测试工程师，解决功能验证、平面布置图设计、时序优化/收敛、可测试设计和芯片测试方面的问题。 职位要求： 1.硕士及以上学历，电子工程或计算机科学相关专业； 2. 熟悉RTL Coding/UVM（Verilog/SystemVerilog）； 3.熟悉ASIC的设计流程，特别是从规格文档到架构定义，再到RTL实现、验证和综合； 4.熟练应用EDA工具（Synopsys或Cadence）：VCS、Xcelium、DC、PT等； 5. 熟悉C/C++语言、Perl、Python等脚本语言；6. 熟悉SOC片上总线协议如AMBA、NOC的优先； 7. 有ARM、RISC-V、GPU、DSP、VPU、NPU、ISP、DisplayIP等处理器设计背景优先； 8. 有USB、PCIe、CXL、UCIe、Ethernet、DDR、UFS、DP等接口背景的优先； 9.有相关AI辅助设计及机器学习在IC设计中应用经验者优先； 10. 富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：上海/成都/南京/广州Title: ASIC Design/Verification Engineer Responsibilities: 1. Independentlywork on the design of ASIC functional blocks in terms of requirement analysis,architecture definition, block design, logic synthesis, and timing analysis(STA). 2. Independently work on the verification of ASIC functional blocks interms of verification plan, test bench building up, test case development, andother related tasks. 3. Perform logic synthesis and timing analysis of chipsand sub-blocks, as well as DFT RTL coding, scan chain/MBIST/boundary scancircuits insertion, and test pattern generation and simulation. 4. Work closelywith system engineers, physical implementation designers, and testing engineersto complete functional verification, floorplan design, timingoptimization/closure, and DFT & ATE testing. Requirements: 1. Master's or abovedegree in EE/CS related majors. 2. Familiar with RTL coding/UVM(Verilog/SystemVerilog). 3. Familiar with the ASIC design flow, includingspecification, architecture definition, RTL coding, verification, andsynthesis. 4. Adept at EDA tools (Synopsys or Cadence), such as VCS, Xcelium,DC, PT. 5. Familiar with C/C++, Perl, Python, or other programming language. 6.A knowledge of SOC on-chip bus protocols (AMBA/NOC) is a plus. 7. A knowledgeof processor design (ARM, RISC-V, GPU, DSP, VPU, NPU, ISP, Display IP) is aplus. 8. A knowledge of interfaces such asUSB/PCIe/CXL/UCIe/Ethernet/DDR/UFS/DP is a plus. 9. Experience in AI-assisteddesign and ML applications in IC design is a plus. 10. Self-motivated and agood team player. Good communication skills in both Chinese and English ineither listening, speaking, reading or writing. Location:Shanghai/Chengdu/Nanjing/Guangzhou

职位名称：模拟电路设计工程师 职位描述： 根据个人情况和公司项目规划，承担如下一种或多种职责： 1.设计开发CMOS深亚微米模拟集成电路，包括电源管理、高速接口、模拟前端电路等； 2.负责通用IO库和定制IO的电路设计，提供全芯片ESD防护解决方案，PAD位置摆放以及ESD的检查； 3.指导版图设计，协助设计测试板，调试验证测试芯片，撰写相关技术文档。 职位要求： 1. 硕士及以上学历，微电子、电子工程相关专业； 2.熟悉相关的EDA工具，了解Linux基础知识； 3.有以下单项或多项经验者优先：Bandgap、LDO、DC-DC等电源管理；VCO、PLL、DLL、PCIE、USB等高速电路；各种数模/模数转换器； 4.有相关AI辅助设计及机器学习在IC设计中应用经验者优先； 5. 富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：上海/成都 Title:Analog Circuit Design Engineer Responsibilities: You will be in a positionresponsible for one or more of below assignments: 1. Devise and develop deepsub-micron CMOS analog integrated circuits, including power management,high-speed interface and analog front-end circuits. 2. Design GPIO library andcustomization IO, provide ESD protection strategy/guideline, PAD cellassignment and ESD review for whole chip. 3. Guide and/or supervise layout.Assist in the design of test boards so as to debug and verify test chips. Writetechnical documents. Requirements: 1. Master's or above degree in Micro-E, EEor related majors. 2. Basic knowledge and skills of Linux and EDA tools. 3.Have experience on one or some of the following disciplines: Bandgap, LDO,DC-DC; VCO, PLL, DLL, PCIE, USB; ADC, DAC, etc. 4. Experience withAI/ML-assisted circuit design tools is a plus. 5. Self-motivated and a goodteam player. Good communication skills in both Chinese and English in eitherlistening, speaking, reading or writing. Location: Shanghai/Chengdu

职位名称：射频集成电路设计工程师 职位描述： 1. 设计CMOS/FDSOI无线IC芯片的射频模拟电路； 2. 指导、监督高质量版图设计； 3.协助设计测试板，调试测试芯片，根据测试结果迭代改进方案。 职位要求： 1. 电子或微电子专业硕士/博士学历； 2. 扎实的相关课程知识及项目经验； 3.有以下设计经验优先： 射频transceiver电路，如BLE、WIFI、NBIoT、GNSS；PA、LNA、MIXER、PLL、VCO、Filter、VGA/PGA、AD/DA、Low Power PMU、XO等； 4.有测试仪器使用经验，如示波器、频谱分析仪、信号源等； 5. 能够熟练使用AI工具辅助研发工作； 6. 富有事业心和团队合作精神，良好的中英文听说读写能力。工作地点：成都/南京 Title: RFIC Design Engineer Responsibilities: 1. Design RF Analogfront-end circuits based on CMOS/FDSOI technology for wireless IC chips. 2.Guide and/or supervise layout designers for high-quality layout. 3. Assist intest board design, debug and verify test chips, and iterate design based on thetest results to optimize the function and performance. Requirements: 1.Master's or PhD degree in EE or Micro-Electronics. 2. Solid course knowledgeand project experience in related areas. 3. Experience in design of thefollowing circuits is preferred: RF transceiver systems: BLE, WIFI, NBIoT,GNSS, etc. PA, LNA, MIXER, PLL, VCO, Filter, VGA/PGA, AD/DA, Low Power PMU, XO,etc. 4. Capability to operate test instruments, including oscilloscope,spectrum analyzer, and signal generator. 5. Experience in AI-assisted tools forIC design is a plus. 6. Self-motivated and a good team player. Goodcommunication skills in both Chinese and English in either listening, speaking,reading or writing. Location: Chengdu/Nanjing

职位名称：编译器工程师 职位描述： 1. 负责为Verisilicon的(GP)GPU等IP设计、开发和维护前端和后端编译器，参与AI编译器的建设； 2.分析编译器所产生代码，提出编译器优化方案； 3. 与硬件和架构部门、系统软件部门密切合作，理解硬件和软件的需求，从编译器角度参与硬件和软件系统的设计。职位要求： 1. 硕士及以上学历，计算机相关专业； 2. 扎实的C/C++编程能力和数据结构和算法知识； 3. 优秀的线性代数知识； 4.有编译器开发经验者优先考虑； 5. 对LLVM和GCC熟悉者优先考虑； 6. 熟悉CPU/(GP)GPU等体系结构者优先考虑； 7. 熟练使用AI者优先；8. 富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：上海/成都 Title: Compiler EngineerResponsibilities: 1. Design, develop and maintain front-end and back-endcompilers for (GP)GPU or other IPs, as well as AI compilers. 2. Analyze thecompiler-generated codes and provide solutions to optimizing compilers. 3. Workclosely with hardware, architecture and software teams to clarify hardware andsoftware requirements. Participate in hardware and software design from thecompiler's perspective. Requirements: 1. Master's or above degree in CS relatedmajors. 2. Strong C/C++ programming skill and solid knowledge of data structureand algorithm. 3. Excellent knowledge of linear algebra. 4. Experience incompiler development is a plus. 5. Familiarity with LLVM/GCC is a plus. 6.Familiarity with CPU/(GP)GPU architecture is a plus. 7. Proficiency in AI is aplus. 8. Self-motivated and a good team player. Good communication skills inboth Chinese and English in either listening, speaking, reading or writing.Location: Shanghai/Chengdu

职位名称：数字后端设计工程师 职位描述： 根据个人情况和公司项目规划，承担如下一种或多种职责： 1.完成编写时序约束，编写低功耗设计文件（UPF/CPF），逻辑综合/物理综合，形式验证，静态时序分析，功耗分析，低功耗设计规则检查（CLP）； 2.完成布局规划，电源规划，布图布线，物理验证，电压降分析，电迁移分析； 3.完成DFT逻辑设计和验证，完成编写DFT模式时序约束，帮助DFT模式时序收敛，帮助芯片bring-up，完成测试向量的调试，良率的提升； 4.探索并引入AI/ML辅助EDA工具（如智能时序预测、自动布局优化、功耗智能调优等），提升后端设计流程的效率与结果质量； 5.参与或主导基于机器学习的数据分析项目，辅助参数预测、异常检测或时序建模等； 6. 为客户/现场应用工程师/销售人员提供技术支持。 职位要求： 1.电子工程硕士或更高学历； 2. 具备以下单项或多项经验：从RTL到GDS的设计实现，芯片级测试，ASIC编码和模拟，ASIC物理版图，集成电路制造和工艺；3. 对人工智能/机器学习在芯片设计中的应用有兴趣或实践经验（如使用过ML工具包、了解时序/功耗预测模型、自动化脚本优化等）； 4.具备基础的数据处理和编程能力 （如Python/Tcl/Perl）， 能够利用AI框架 （如TensorFlow/PyTorch）进行简单的模型训练或推理；5. 能够熟练使用AI工具辅助研发工作者优先； 6. 富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：上海/成都/南京 Title:Physical Design Engineer Responsibilities: You will be in a positionresponsible for one or more of below assignments: 1. Complete writing timingconstraint, writing UPF/CPF, logic/physical synthesis, formal verification,STA, power analysis, CLP. 2. Complete floorplan, power plan, P&R, physicalverification, IRDrop analysis, EM analysis. 3. Complete DFT logic design andverification, writing DFT mode timing constraint, support DFT mode timingclosure, support chip bring-up, complete test pattern debugging and yieldimprovement. 4. Explore and introduce AI/ML assisted EDA tools (e.g.,intelligent timing prediction, automated placement optimization, smart powertuning) to improve the efficiency and quality of the physical design flow. 5.Participate in or lead machine learning based data analytics projects tosupport parameter prediction, anomaly detection, and timing modeling, amongothers. 6. Provide technical support for customer/FAE/sales. Requirements: 1.Master's or above degree in EE. 2. Have following single or multipleexperiences: design implementation from RTL to GDS, chip level testing, ASICcoding and simulation, ASIC physical layout, IC manufacture and process. 3.Interest or hands-on experience in applying AI/ML to chip design (e.g., usingML toolkits, understanding timing/power prediction models, automated scriptoptimization). 4. Basic data processing and programming skills (e.g.,Python/Tcl/Perl), with the ability to use AI frameworks (e.g.,TensorFlow/PyTorch) for simple model training or inference. 5. Familiarity withAI tools applied in R&D is preferred. 6. Self-motivated and a good team player.Good communication skills in both Chinese and English in either listening,speaking, reading or writing. Location: Shanghai/Chengdu/Nanjing

职位名称：模拟电路设计工程师 职位描述： 根据个人情况和公司项目规划，承担如下一种或多种职责： 1.设计开发CMOS深亚微米模拟集成电路，包括电源管理、高速接口、模拟前端电路等； 2.负责通用IO库和定制IO的电路设计，提供全芯片ESD防护解决方案，PAD位置摆放以及ESD的检查； 3.指导版图设计，协助设计测试板，调试验证测试芯片，撰写相关技术文档。 职位要求： 1. 硕士及以上学历，微电子、电子工程相关专业； 2.熟悉相关的EDA工具，了解Linux基础知识； 3.有以下单项或多项经验者优先：Bandgap、LDO、DC-DC等电源管理；VCO、PLL、DLL、PCIE、USB等高速电路；各种数模/模数转换器； 4.有相关AI辅助设计及机器学习在IC设计中应用经验者优先； 5. 富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：上海/成都 Title:Analog Circuit Design Engineer Responsibilities: You will be in a positionresponsible for one or more of below assignments: 1. Devise and develop deepsub-micron CMOS analog integrated circuits, including power management,high-speed interface and analog front-end circuits. 2. Design GPIO library andcustomization IO, provide ESD protection strategy/guideline, PAD cellassignment and ESD review for whole chip. 3. Guide and/or supervise layout.Assist in the design of test boards so as to debug and verify test chips. Writetechnical documents. Requirements: 1. Master's or above degree in Micro-E, EEor related majors. 2. Basic knowledge and skills of Linux and EDA tools. 3.Have experience on one or some of the following disciplines: Bandgap, LDO,DC-DC; VCO, PLL, DLL, PCIE, USB; ADC, DAC, etc. 4. Experience withAI/ML-assisted circuit design tools is a plus. 5. Self-motivated and a goodteam player. Good communication skills in both Chinese and English in eitherlistening, speaking, reading or writing. Location: Shanghai/Chengdu

职位名称：数字前端设计/验证工程师 职位描述： 1. 独立完成ASIC功能模块的设计任务，包括：需求分析，架构定义，模块设计，逻辑综合和时序分析； 2.独立完成ASIC功能模块的验证任务，包括：制定验证方案，搭建测试环境，编写测试用例等； 3. 负责芯片顶层及子模块的逻辑综合和时序分析；以及相关DFTRTL代码编写，扫描链，MBIST电路，边界扫描电路插入，以及测试pattern的生成及仿真等； 4.作为芯片的设计者，配合系统工程师、物理实现工程师和测试工程师，解决功能验证、平面布置图设计、时序优化/收敛、可测试设计和芯片测试方面的问题。 职位要求： 1.硕士及以上学历，电子工程或计算机科学相关专业； 2. 熟悉RTL Coding/UVM（Verilog/SystemVerilog）； 3.熟悉ASIC的设计流程，特别是从规格文档到架构定义，再到RTL实现、验证和综合； 4.熟练应用EDA工具（Synopsys或Cadence）：VCS、Xcelium、DC、PT等； 5. 熟悉C/C++语言、Perl、Python等脚本语言；6. 熟悉SOC片上总线协议如AMBA、NOC的优先； 7. 有ARM、RISC-V、GPU、DSP、VPU、NPU、ISP、DisplayIP等处理器设计背景优先； 8. 有USB、PCIe、CXL、UCIe、Ethernet、DDR、UFS、DP等接口背景的优先； 9.有相关AI辅助设计及机器学习在IC设计中应用经验者优先； 10. 富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：上海/成都/南京/广州Title: ASIC Design/Verification Engineer Responsibilities: 1. Independentlywork on the design of ASIC functional blocks in terms of requirement analysis,architecture definition, block design, logic synthesis, and timing analysis(STA). 2. Independently work on the verification of ASIC functional blocks interms of verification plan, test bench building up, test case development, andother related tasks. 3. Perform logic synthesis and timing analysis of chipsand sub-blocks, as well as DFT RTL coding, scan chain/MBIST/boundary scancircuits insertion, and test pattern generation and simulation. 4. Work closelywith system engineers, physical implementation designers, and testing engineersto complete functional verification, floorplan design, timingoptimization/closure, and DFT & ATE testing. Requirements: 1. Master's or abovedegree in EE/CS related majors. 2. Familiar with RTL coding/UVM(Verilog/SystemVerilog). 3. Familiar with the ASIC design flow, includingspecification, architecture definition, RTL coding, verification, andsynthesis. 4. Adept at EDA tools (Synopsys or Cadence), such as VCS, Xcelium,DC, PT. 5. Familiar with C/C++, Perl, Python, or other programming language. 6.A knowledge of SOC on-chip bus protocols (AMBA/NOC) is a plus. 7. A knowledgeof processor design (ARM, RISC-V, GPU, DSP, VPU, NPU, ISP, Display IP) is aplus. 8. A knowledge of interfaces such asUSB/PCIe/CXL/UCIe/Ethernet/DDR/UFS/DP is a plus. 9. Experience in AI-assisteddesign and ML applications in IC design is a plus. 10. Self-motivated and agood team player. Good communication skills in both Chinese and English ineither listening, speaking, reading or writing. Location:Shanghai/Chengdu/Nanjing/Guangzhou

职位名称：软件工程师 职位描述： 根据个人情况及公司发展规划，承担如下职责之一： 1.负责GPU/GPGPU/NPU/VPU/ISP/ZSP/DPU/Security IP/Interface IP/CommunicationIP的软件设计、开发和优化工作； 2. 负责各种IP C模型的建模工作； 3.负责上层AI软件框架的适配及开发工作，提升AI模型在GPU/GPGPU/NPU处理器上的性能； 4.参与Windows/Android/Linux/Chromium/嵌入式SDK的软件测试与自动化等工作。 职位要求： 满足两种或以上条件者优先考虑： 1.计算机、通信工程、信息工程、电子工程、自动化等相关专业本科及以上学历； 2. 熟悉或精通一门编程语言，具体语言不限，熟悉C/C++，Python等； 3.对操作系统和数据结构有良好的理解； 4. 清楚了解硬件、软件交互和系统级性能分析；了解Linux内核驱动或Windows WDDM驱动开发； 5.理解一种或者一种以上操作系统，有过实际项目开发经验的优先； 6. 熟悉GPU/GPGPU/NPU/VPU/ISP/ZSP/DPU/SecurityIP/Interface IP/Communication IP并有实际项目的开发经验优先； 7.熟悉诸如PyTorch和ONNX框架且对GPU/GPGPU/NPU上AI算子开发经验者优先； 8. 熟悉MLIR/TVM/Triton等AI编译器框架者优先；9. 熟悉DX/OpenGL/Vulkan/OpenCL/CUDA者优先； 10. 熟练使用AI，善于使用AI进行开发； 11.富有事业心和团队合作精神，良好的中英文听说读写能力。 工作地点：成都/南京 Title: Software EngineerResponsibilities: You will be in a position responsible for one of thefollowing assignments: 1. Design, develop and optimize software forGPU/GPGPU/NPU/VPU/ISP/ZSP/DPU/Security IP/Interface IP/Communication IP. 2.Design and develop C-model for different IP processors. 3. Develop VSIproprietary software code to adapt upper-level AI frameworks and enhance theperformance of AI models on GPU/GPGPU/NPU IP processors. 4. Develop devicedrivers and software based on Windows/Android/Linux/Chromium/ FreeRTOS, etc.Conduct automation testi

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